Improving the Soft-error Tolerability of a Soft-core Processor on an FPGA using Triple Modular Redundancy and Partial Reconfiguration

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which can be induced by radiation effects. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. In this work, we propose techniques for SEU mitigation and recovery of a soft-core processor using triple modular redundancy (TMR) and partial reconfiguration (PR) with state synchronization. In addition, we propose a reliability estimation formula for a triplicated circuit by applying combinational probability. By experiment, we confirm that a faulty soft-core processor can be recovered and synchronized with other processors. The proposed technique requires 1.38 times the resource usage and 82.4 % of the operating frequency of the Basic TMR. However, the proposed recovery process only takes 6 μs under TMR and PR. As a result of the reliability estimates, we can reduce the failure in time (FIT) of the system by 23.7 % from the Basic TMR.